This invention relates to semiconductor devices, and is more in particular directed to the provision of a thin film transistor arrangement especially adapted for addressing the elements of a liquid crystal display.
In general, matrix addressing techniques for liquid crystal displays can be classified as employing either a multiplexing matrix or an active matrix. In an active matrix a stitching device is provided at each pixel of the display. This switching device can be a two terminal device, such as a metal-insulator-metal device (MIM), a back-to-back diode, or diode ring, or a three terminal device, such as a thin film transistor (TFT). The circuit design in the display panel employing two terminal devices is simpler than for three terminal devices. The gray scale controllability for achieving better image quality in the two terminal devices, however, is inferior to that achieved with three terminal devices. Therefore, in order to achieve high quality of reproduction in flat panel LCD TV displays, it is desirable to use thin film transistor devices.
As the display size, and hence the number of pixels, increases, the yield of TFT arrays drastically decreases due to various defects produced during the TFT fabrication process. For large flat panel displays, the number of gate and source bus lines increases and also the total line length of both bus lines increases substantially. The occurrence of defects such as discontinuities in the bus line also increases. It is therefore desirable to provide a panel circuit design that improves the LCD yield in such arrangements.
FIG. 1 illustrates the structure of a known TFT LCD addressing system with one TFT 1a for each pixel 1b. In the illustrated circuit, if, for example, the gate line (1c) is open, then the pixels starting from the defective point will not receive any signal and these pixels will be off all of the time. This will cause a line defect that can be easily distinguished by human eyes.
To solve this problem, various redundant structures have been proposed. For example, Matsushita Electric, Japan Display 86, p204-207, suggests the structure illustrated in FIG. 2, wherein each pixel responds to a pair of TFT's 2a controlled by the adjacent scanning gate lines 2b. In this arrangement, no additional gate or source lines 2c are necessary. When gate line 2d is open, the pixels between the gate line 2d and the adjacent gate line 2e will also receive the signals which are controlled by the gate line 2e, unless the gate line 2e is also defective. Therefore, the line defect caused by the open gate line can be eliminated by using this two transistor structure. The pixel open ratio in this display structure decreases, however, due to the increase in the area occupied by the TFT. The pixel open ratio is defined as the pixel area which can be lit in proportion to the whole display area. When the pixel open ratio decreases, display qualities such as brightness, color, etc., become degraded.
In order to reduce TFT junction leakage current, the dual gate structure shown in FIG. 3 may be used. The two TFT's 3a are connected in series as switch devices. If this dual gate structure is combined with the arrangement illustrated in FIG. 2, the arrangement of FIG. 4 will result, wherein the pixel open ratio of this LCD panel is significantly decreased.
European Patent Application document EP No. 182645 also discloses the circuit arrangement for a liquid crystal display as shown in FIG. 2 of the present application, as well as other arrangements employing two or three transistors for each pixel. The reference discloses further arrangements wherein transistors are connected so that a common junction occurs between the source/drain electrodes of four transistors, with two of the remaining source/drain electrodes being connected to the same signal line and the remaining source/drain elements being connected to separate pixel elements.
In further known art, Patent Document EP No. 102296 discloses interconnections of matrices, which may include thin film transistors; patent document EP No. 196915 describes a thin film transistor array that is limited to the structure of the individual transistors: and Patent Document EP No. 85402489 discloses an array. As will be apparent, these references do not suggest the structure and concept of the present invention.